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xr-2212 ...the analog plus company tm precision phase-locked loop rev. 2.01 1979 exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 1 june 1997-3 features quadrature vco outputs wide frequency range (0.01hz to 300khz) wide supply voltage range (4.5v to 20v) ttl/hcmos compatible (v cc = 5vdc) wide dynamic range (2mv to 3vrms) adjustable tracking range ( 1% to 80%) excellent temp. stability 20ppm/ c, typ. applications frequency synthesis data synchronization fm detection tracking filters fsk demodulation general description the xr-2212 is an ultra-stable monolithic phase-locked loop (pll) system especially designed for data communications and control system applications. its on board reference and uncommitted operational amplifier, together with a typical temperature stability of better than 20ppm/ c, make it ideally suited for frequency synthesis, fm detection, and tracking filter applications. the wide input dynamic range, large operating voltage range, large frequency range, and hcmos and ttl compatibility contribute to the usefulness and wide applicability of this device. ordering information part no. package operating temperature range xr-2212m 16 lead 300 mil cdip -55 c to +125 c xr-2212cp 16 lead 300 mil pdip 0 c to +70 c xr-2212p 16 lead 300 mil pdip -40 c to +85 c block diagram 2 inp 1 v cc 4 gnd 10 0-det o 8 out 6 comp 11 v ref 5 vcoov 3 vcooc 15 vcoqo 12 tim r 14 tim c1 13 tim c2 16 0-det i 9 pinp 7 ninp figure 1. xr-2212 block diagram pre amplifier phase detector op amp v ref amp vco
xr-2212 2 rev. 2.01 pin configuration 1 16 lead pdip, cdip (0.300o) v cc inp vcooc 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 tim r tim c2 tim c1 vcoqo 0-det i gnd vcoov comp ninp out pinp 0-det o v ref pin description pin # symbol type description 1 v cc positive power supply. 2 inp i receive analog input. 3 vcooc o vco current output. 4 gnd ground pin. 5 vcoov o vco voltage source output. 6 comp i uncommitted amplifier, frequency compensation input. 7 ninp i inverted input. uncommitted amplifier. 8 out o uncommitted amplifier output. 9 pinp i positive input. uncommitted amplifier. 10 0-det o o phase detector output. 11 v ref o internal voltage reference. the value of v ref is v cc /2 -650mv. 12 tim r i timing resistor input. this pin connects to the timing resistor of the vco. 13 tim c2 i timing capacitor input. the timing capacitor connects between this pin and pin 14. 14 tim c1 i timing capacitor input. the timing capacitor connects between this pin and pin 13. 15 vcoqo o vco quadrature output. 16 0-det i i phase detector input.
xr-2212 3 rev. 2.01 electrical characteristics test conditions: v cc = +12v, t a = + 25 c, r 0 = 30k , c 0 = 0.033 f , unless otherwise specified. see figure 3 for component designation. pt xr-2212m/2212p xr-2212cp uit c diti p arameter min. typ. max. min. typ. max. u n i ts c on di t i ons general characteristics supply voltage 4.5 15 4.5 15 v supply current 6 10 6 12 ma r 0 > 10k ., see figure 5 oscillator section frequency accuracy + 1 + 3 + 1 % deviation from f 0 = 1/r 0 c 0 frequency stability r 1 = temperature 1 + 20 + 50 + 20 ppm/ c see figure 9 power supply 0.05 0.5 0.05 %/v v cc = 12 + 1v, see figure 8 0.2 0.2 %/v v cc = 5 + 0.5v, see figure 8 upper frequency limit 100 300 300 khz r 0 = 8.2k , c 0 = 400pf lowest practical operating f 0.01 0.01 hz r 0 = 2m , c 0 = 50 f f requency timing resistor, r 0 see figure 5 operating range 5 2000 5 2000 k recommended range 15 100 15 100 k see figure 8 and figure 9 oscillator outputs voltage output measured at pin 5 positive swing, v oh 11 11 v negative swing, v ol 0.4 0.8 0.5 v current sink capability 1 1 ma current output measured at pin 3 peak current swing 100 150 150 a output impedance 1 1 m quadrature output measured at pin 15 output swing 0.6 0.6 v dc level 0.3 0.3 v referenced to pin 11 output impedance 3 3 k loop phase detector section measured at pin 10 peak output current + 150 + 200 + 300 + 100 + 200 + 300 a output offset current + 1 + 2 a output impedance 1 1 m maximum swing + 4 + 5 + 4 + 5 v referenced to pin 11 notes 1 for xr-2212p the parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production. bold face parameters are covered by production test and guaranteed over operating temperature range.
xr-2212 4 rev. 2.01 electrical characteristics (cont'd) parameter xr-2212m/2212p xr-2212cp units conditions p arame t er min. typ. max. min. typ. max. u n it s c on diti ons input preamp section measured at pin 2 input impedance 20 20 k input signal to cause limiting 2 10 2 mv rms op amp section voltage gain 55 70 55 70 db r l = 5.1k , r f = input bias current 0.1 1 0.1 1 a offset voltage + 5 + 20 + 5 + 20 mv slew rate 2 2 v/ sec internal reference measured at pin 11 voltage level 4.9 5.3 5.7 4.75 5.3 5.85 v output impedance 100 100 ac small signal maximum source current 80 80 a notes 1 for xr-2212p the parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production. bold face parameters are covered by production test and guaranteed over operating temperature range. specifications are subject to change without notice absolute maximum ratings power supply 18v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input signal level 3v rms . . . . . . . . . . . . . . . . . . . . . . . . power dissipation: ceramic package: 750mw . . . . . . . . . . . . . . . . . . . . . . . derate above t a = + 25 c 6mw/ c . . . . . . . . plastic package: 625mw . . . . . . . . . . . . . . . . . . . . . . . . derate above t a = + 25 c 5mw/ c . . . . . . . . system description the xr-2212 is a complete pll system with buffered inputs and outputs, an internal reference, and an uncommitted op amp. two vco outputs are pinned out; one sources current, the other sources voltage. this enables operation as a frequency synthesizer using an external programmable divider. the op amp section can be used as an audio preamplifier for fm detection or as a high speed sense amplifier (comparator) for fsk demodulation. the center frequency, bandwidth, and tracking range of the pll are controlled independently by external components. the pll output is directly compatible with cmos, hcmos and ttl logic families as well as microprocessor peripheral systems. the precision pll system operates over a supply voltage range of 4.5v to 20v, a frequency range of 0.01hz to 300khz, and accepts input signals in the range of 2mv to 3v rms. temperature stability of the vco is typically better than 20 ppm/ c with the optimum timing resistor value.
xr-2212 5 rev. 2.01 + - op amp phase detector loop filter pre amp 0-det input signal input amp vco voltage output vco current output vco phase quadrature output figure 2. functional block diagram of xr-2212 precision pll system v cc 8 c o r l 5.6k demod output 6 c 1 10 r f 9 7 r c 0.1 f input signal 2 phase detector 16 5 %n 0.1 f external divider (optional) vco 14 13 12 r 1 r 0 c o 0.1 f r 3 11 internal reference figure 3. generalized circuit connection for fm detection, signal tracking or frequency synthesis
xr-2212 6 rev. 2.01 reference output voltage 11 vcc 1 loop detector 10 output phase phase detector 16 input 30k 30k signal input 2 non inv inp 9 amp out 8 internal voltage reference vco out 5 phase detector 2k a a1 input preamplifier 2k a 14 13 a1 timing capacitor 5k 5k timing resistor 12 5k 5k vco quad out 15 vco current output 3 inv inp 7 comp 6 gnd 4 op amp figure 4. simplified circuit schematic of xr-2212 c 0 r o
xr-2212 7 rev. 2.01 typical characteristics ( f ) figure 5. typical supply current vs. v cc (logic outputs open circuited) figure 6. vco frequency vs. timing resistor figure 7. vco frequency vs. timing capacitor figure 8. typical f 0 vs. power supply characteristics supply voltage v cc (v) supply current (ma) 0 5 10 15 20 r l = 5k r l = 10k r l > 100k 4 6 8 1012 1416 182022 24 10 0.1 0.01 100 1000 10,000 r 0 (k ) f 0 (hz) 4 6 81012141618202224 1000 10,000 0 10 100 1000 c 0 normalized frequency f 0 = 1khz r > 10r 0 curve r 0 1 2 3 4 5 5k 10k 30k 100k 300k 5 4 3 2 1 1 2 3 4 5 c 0 =0.001 f c 0 =0.0033 f c 0 =0.01 f c 0 =0.033 f c 0 =0.1 f c 0 =0.33 f r 0 =5k r 0 =10k r 0 =40k r 0 =20k r 0 =80k r 0 =160k f 0 (hz) 1.02 1.01 1.00 0.99 0.98 0.97 v cc (v)
xr-2212 8 rev. 2.01 r 0 =10k r 0 =50k r 0 =500k r 0 =1m w 1m w 500k 50k 10k temperature (c) normalized frequency drift (% of f ) o +1.0 +0.5 0 -0.5 -1.0 -50 -25 0 25 50 75 100 125 v cc =12v r 1 =12r 0 f 0 =1khz figure 9. typical center frequency drift vs. temperature description of circuit controls signal input (pin 2): signal is ac coupled to this terminal. the internal impedance at pin 2 is 20k . recommended input signal level is in the range of 10mv to 5v peak-to-peak. vco current output (pin 3): this is a high impedance (m ) current output terminal which can provide + 100 a drive capability with a voltage swing equal to v cc . this output can directly interface with cmos or nmos logic families. vco voltage output (pin 5): this terminal provides a low- impedance ( 50 ) buffered output for the vco. it can directly interface with low-power schottley ttl. for interfacing with standard ttl circuits, a 750 pull-down resistor from pin 5 to ground is required. for operation of the pll without an external divider, pin 5 can be dc coupled to pin 16. op amp compensation (pin 6): the op amp section is frequency compensated by connecting an external capacitor from pin 6 to the amplifier output (pin 8). for unity-gain compensation a 20pf capacitor is recommended. op amp inputs (pins 7 and 9): these are the inverting and the non-inverting inputs for the op amp section. the common-mode range of the op amp inputs is from +1v to (v cc - 1.5) volts. op amp output (pin 8): the op amp output is an open- collector type gain stage and requires a pull-up resistor, r l , to v cc for proper operation. for most applications, the recommended value of r l is in 5k to 10k range. phase detector output (pin 10): this terminal provides a high-impedance output for the loop phase-detector. the pll loop filter is formed by r 1 and c 1 connected to pin 10 (see figure 3 ). with no input signal, or with no phase-error within the pll, the dc level at pin 10 is very nearly equal to v ref . the peak voltage swing available at the phase detector output is equal to v ref . reference voltage, v ref (pin 11): this pin is internally biased at the reference voltage level. v ref :v ref = v cc /2 - 650mv. the dc voltage level at this pin forms an internal reference for the voltage levels at pins 10, 12 and 16. pin 1 must be bypassed to ground with a 0.1 f capacitor, for proper operation of the circuit. vco control input (pin 12): vco free-running frequencies determined by external timing resistor, r 0 , connected from this terminal to ground. for optimum temperature stability, r 0 must be in the range of 10k to 100k (see figure 9 ). vco frequency adjustment: vco can be fine-tuned by connecting a potentiometer, r x , in series with r 0 at pin 12 (see figure 11 ). this terminal is a low-impedance point, and is internally biased at a dc level equal to v ref . the maximum timing
xr-2212 9 rev. 2.01 current drawn from pin 12 must be limited to < 3 ma for proper operation of the circuit. vco timing capacitor (pins 13 and 14): vco frequency is inversely proportional to the external timing capacitor, c 0 , connected across these terminals (see figure 6 ). c 0 must be nonpolar, and in the range of 200pf to 10 f. vco quadrature output (pin 15): the low-level ( 0.6vpp) output at this pin is at quadrature phase (i.e. 90 phase-offset) with the other vco outputs at pins 3 and 5. the dc level at pin 15 is approximately 300mv above v ref . the quadrature output can be used with an external multiplier as a alock detecto circuit. in order not to degrade oscillator performance, the output at pin 15 must be buffered with an external high impedance low capacitance amplifier. when not in use, pin 15 should be left open-circuited. phase detector input (pin 16): voltage output of the vco (pin 5) or the output of an external frequency divider is connected to this pin. the dc level of the sensing threshold for the phase detector is referenced to v ref . if the signal is capacitively coupled to pin 16, then this pin must be biased from pin 11, through an external resistor, r b (r b 10k ). the peak voltage swing applied to pin 16 must not exceed (v cc - 1.5) volts. phase-locked loop parameters transfer characteristics figure 10 shows the basic frequency to voltage characteristics of xr-2212. with no input signal present, filtered phase detector output voltage is approximately equal to the internal reference voltage, v ref at pin 11. the pll can track an input signal over its tracking bandwidth, shown in the figure. the frequencies f tl and f th represent the lower and the upper edge of the tracking range, f 0 represents the vco center frequency. note output voltage is referenced to internal reference voltage v ref at pin 11 figure 10. phase detector output voltage (pin 10) as a function of input signal frequency input signal frequency frequency tracking bandwidth f f 0 v r 2v r f tl f o f th phase detector output (pin 10)
xr-2212 10 rev. 2.01 design equations (see figure 3 and figure 10 for definition of components.) 1. vco center frequency, f 0 : f 0 = 1/r 0 c 0 hz 2. internal reference voltage, v ref (measured at pin 11) v ref = v cc /2 - 650mv 3. loop low-pass filter time constant, : = r 1 c 1 4. loop damping, : 0.25 nc 0 c 1 where n is the external frequency divider modular (see 2). if no divider is used, n = 1. 5. loop tracking bandwidth, f/f 0 : f/f 0 = r 0 /r 1 6. phase detector conversion gain, k : (k is the differential dc voltage across pins 10 and 11, per unit of phase error at phase-detector input) k = -2v ref / volts/radian 7. vco conversion gain, k 0 : (k 0 is the amount of change in vco frequency, per unit of dc voltage change at pin 10. it is the reciprocal of the slope of conversion characteristics shown in figure 10 ). k 0 = -1/v ref c 0 r 1 hz/v 8. total loop gain, k t k t = 2 k k 0 = 4/c 0 r 1 rad/sec/volt 9. peak phase-detector current, i a ; available at pin 10. i a = v ref (volts)/25ma application information fm demodulation xr-2212 can be used as a linear fm demodulator for both narrow-band and wide-band fm signals. the generalized circuit connection for this application is shown in figure 11 , where the vco output (pin 5) is directly connected to the phase detector input (pin 16). the demodulated signal is obtained at phase detector output (pin 10). in the circuit connection of figure 10, the op amp section of xr-2212 is used as a buffer amplifier to provide both additional voltage amplification as well as current drive capability. thus, the demodulated output signal available at the op amp output (pin 8) is fully buffered from the rest of the circuit. in the circuit of figure 11 , r 0 c 0 set the vco center frequency, r 1 sets the tracking bandwidth, c 1 sets the low-pass filter time constant. op amp feedback resistors r f and r c set the voltage gain of the amplifier section.
xr-2212 11 rev. 2.01 0.1 f input 2 fm 4 c 1 phase detector 16 10 1 v cc v cc r f 9 7 r c 8 demod output 6 30pf r l 5k 0.1 f internal reference 0.1 f 11 vco 14 13 12 r 1 r 0 c o 5 rx fine tune figure 11. circuit connection for fm demodulation design instructions the circuit of figure 11 can be tailored to any fm demodulation application by a choice of the external components r 0 , r 1 , r c , r f , c 0 and c 1 . for a given fm center frequency and frequency deviation, the choice of these components can be calculated as follows, using the design equations and definitions given on page 10. a) choose vco center frequency f 0 to be the same as fm carrier frequency. b) choose value of timing resistor r 0 , to be in the range of 10k to 100k . this choice is arbitrary. the recommended value is r 0 20k . the final value of r 0 is normally fine-tuned with the series potentiometer, r x . c) calculate value of c 0 from design equation (1) or from figure 7 : c 0 = 1/r 0 f 0 d) choose r 1 to determine the tracking bandwidth, f (see design equation 5). the tracking bandwidth, f, should be set significantly wider than the maximum input fm signal deviation, f sm . assuming the tracking bandwidth to be ano times larger than f sm , one can re-unite design equation 5 as: f f 0 r 0 r 1 n f sm f 0 table 2. lists recommended values of n, for various values of the maximum deviation of the input fm signal. e) calculate c 1 to set loop damping (see design equation 4). normally, v = 1/2 is recommended. then, c 1 = c 0 /4 for v = 1/2.
xr-2212 12 rev. 2.01 % deviation of fm signal ( f sm /f 0 ) recommended value of bandwidth ratio, n (n = f / f sm ) 1% or less 10 1% to 3% 5 1% to 5% 4 5% to 10% 3 10% to 30% 2 30% to 50% 1.5 table 2. recommended values of bandwidth ratio, n, for various values of fm signal frequency deviation. (note: n is the ratio of tracking bandwidth f to max. signal frequency deviation, f sm ). f) calculate r c and r f to set peak output signal amplitude. output signal amplitude, v out , is given as: v out f sm f 0 ( v ref ) r 1 r 0 r c r f r c in most applications, r f = 100k is recommended; then r c , can be calculated from the above equation to give desired output swing. the output amplifier can also be used as a unity-gain voltage follower, by open circuiting r c (i.e., r c = ). note: all calculated component values except r 0 can be rounded-off to the nearest standard value, and r 0 can be varied to fine-tune center frequency, through a series potentiometer, r x , (see figure 11). design example demodulator for fm signal with 67khz carrier frequency with 5khz frequency deviation. supply voltage is +12v and required peak output swing is 4v. step a) f 0 is chosen as 67khz. step b) choose r 0 = 20k (18k fixed resistor in series with 5k potentiometer). step c) calculate c 0 ; from design equation (1). c 0 = 746pf step d) calculate r 1 . for given fm deviation, f sm /f 0 = 0.0746, and n = 3 from table 2. then: r 0 /r 1 = (3)(0.0746) = 0.224 or: r 1 = 89.3k . step e): calculate c1 = (c 0 /4) = 186pf. step f): calculate r c and r f to get 4v peak output swing: let r f = 100k . then, r c = 80.6k . note: all values except r 0 can be rounded-off to nearest standard value. frequency synthesis figure 12 shows the generalized circuit connection for frequency synthesis. in this application an external frequency divider is connected between the vco output (pin 5) and the phase-detector input (pin 16). when the circuit is in lock, the two signals going into the phase-detector are at the same frequency, or f s = f 1 /n where n is the modulus of the external frequency divider. conversely, the vco output frequency, f 1 is equal to n fs . in the circuit configuration of figure 12 , the external timing components, r 0 and c 0 , set the vco free running frequency; r 1 sets the tracking bandwidth and c 1 sets the loop damping, i.e., the low-pass filter time constant (see design equations). the total tracking range of the pll (see figure 10 ), should be chosen to accommodate the lowest and the highest frequency, f max and f min , to be synthesized. a recommended choice for most applications is to choose a tracking half-bandwidth f, such that: f f max - f min if a variable input frequency and a variable counter modulus n is used, then the maximum and the minimum values of output frequency will be: f max = n max (f s ) max and f min = n min (f s ) min if a fixed output frequency is desired, i.e. n and f s are fixed, then a 10% tracking bandwidth is recommended. excessively large tracking bandwidth may cause the pll to lock on the harmonics of the input signals; and the small tracking range increases the alock-upo or acquisition time. design instructions for a given performance requirement, the circuit of figure 12 can be optimized as follows: a) choose center frequency, f 0 , to be equal to the output frequency to be synthesized. if a range of output
xr-2212 13 rev. 2.01 frequencies is desired, set f 0 to be at mid-point of the desired range. b) choose timing resistor r 0 to be in the range of 15k to 100k . this choice is arbitrary. r 0 can be fine tuned with a series potentiometer, r x . c) choose timing capacitor, c 0 from figure 7 or equation 1. d) calculate r 1 to set tracking bandwidth (see figure 10 and design equation 5). if a range of output frequencies are desired, set r 1 to get: f = f max - f min if a single fixed output frequency is desired, set r 1 to get: f = 0.1 f 0 e) calculate c 1 to obtain desired loop damping. (see design equation 4). for most applications, v = 1/2 is recommended, thus: c 0 = nc 0 /4 note all component values except r 0 can be rounded off to the nearest standard value. 9 7 8 6 1 v cc c 1 0.1 f 0.1 f 2 phase detector 10 input signal output f1 = nfs vco 14 13 16 5 %n f o = f1/n 74ls90 or similar 4 1k 12 r 1 r 0 internal reference 11 0.1 f c o figure 12. circuit connection for frequency synthesizer v cc
xr-2212 14 rev. 2.01 input sensitivity the input to the xr-2212 may sometimes be too sensitive to noise conditions on the input line. figure 13 illustrates a method of de-sensitizing the xr-2212 from such noisy line conditions by the use of a resistor, rx, connected from pin 2 to ground. the value of rx is chosen by the equation and the desired minimum signal threshold level. v in minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting v threshold). v in minimum ( peak ) v a v b v 2.8 v offset v ref 20, 000 (20, 000 r x ) or r x 20, 000 v ref v 1 ?? ?? ?? vcc rx input 2 20k va 20k to phase detector vb v ref 11 figure 13. desensitizing input stage
xr-2212 15 rev. 2.01 a 0.100 0.200 2.54 5.08 a 1 0.015 0.060 0.38 1.52 b 0.014 0.026 0.36 0.66 b 1 0.045 0.065 1.14 1.65 c 0.008 0.018 0.20 0.46 d 0.740 0.840 18.80 21.34 e 1 0.250 0.310 6.35 7.87 e 0.300 bsc 7.62 bsc e 0.100 bsc 2.54 bsc l 0.125 0.200 3.18 5.08 a 0 15 0 15 d b e b 1 16 lead ceramic dual-in-line (300 mil cdip) rev. 1.00 symbol min max min max inches millimeters 18 9 a c e 1 a l a 1 seating plane base plane 16 e note: the control dimension is the inch column
xr-2212 16 rev. 2.01 16 lead plastic dual-in-line (300 mil pdip) rev. 1.00 16 1 9 8 d e b 1 a 1 e 1 e a l b seating plane symbol min max min max inches a 0.145 0.210 3.68 5.33 a 1 0.015 0.070 0.38 1.78 a 2 0.115 0.195 2.92 4.95 b 0.014 0.024 0.36 0.56 b 1 0.030 0.070 0.76 1.78 c 0.008 0.014 0.20 0.38 d 0.745 0.840 18.92 21.34 e 0.300 0.325 7.62 8.26 e 1 0.240 0.280 6.10 7.11 e 0.100 bsc 2.54 bsc e a 0.300 bsc 7.62 bsc e b 0.310 0.430 7.87 10.92 l 0.115 0.160 2.92 4.06 a 0 15 0 15 millimeters a a 2 c note: the control dimension is the inch column e b e a
xr-2212 17 rev. 2.01 notes
xr-2212 18 rev. 2.01 notes
xr-2212 19 rev. 2.01 notes
xr-2212 20 rev. 2.01 notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1979 exar corporation datasheet june 1997 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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